1. Field of the Invention
This invention relates to a method for planarizing dielectric films between conductive layers on semiconductor wafers which are for use in the fabrication of integrated circuits.
2. Description of the Prior Art
The increase of circuit density on silicon chips necessitates increased ability to interconnect large numbers of integrated silicon devices on a single chip.
The dimensional limitation of the active area in an integrated circuit dictates that vertical interconnections are made by means of multilevel metallization. As the circuits become denser and the feature sizes smaller, to topography becomes too sever for conventional multilevel metallization structures to provide acceptable yield or to have acceptable reliability. One way to remove the topography in order to planarize a particular metallization level, is the etch back process. Japanese Patent Lay-Open No. 225526/1984 discloses the etch back process, which comprises forming a dielectric film over the mesa-like portions and the trench region, forming a polymer layer over said dielectric film, which is a polystyrene having a molecular weight of about 100,000, reducing the viscosity of said polymer layer under baking to decrease the initial step height, hardening said polymer by Ultra-Violet or deep-Ultra-Violet irradiation and dry-etching said polymer layer to transfer the polymer surface to said dielectric film. FIG. 1 shows a relationship of pattern width and step height after leveling the polystyrene, which has a molecular weight of 100,000, by baking at 200.degree. C. for an hour under N.sub.2 flow condition. The initial step height is 6000 .ANG.. With increasing pattern width, step height increases and is almost the same as the initial step height at step width of 40 .mu.m.